Embedded Executive Podcast Embedded Executive: RISC-V Works Great At Low Power Levels, Too | Upbeat Technology
Nov 19, 2025
Jerry Chen, founder and CEO of Upbeat Technology, is a low-power RISC-V SoC specialist who previously worked on CPU pipelines and with SiFive. He explains why Upbeat targets ultra-low-power markets like wearables and always-on IoT. He discusses RISC-V's power advantages, the SiFive partnership, licensing cores versus building them, tape-out experience, benchmarks, and tooling trade-offs.
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Escaping The 'ARM CPU Core Cage'
- Jerry chose RISC-V over ARM to avoid being trapped in an 'ARM CPU core cage' and to differentiate his SoC.
- His Intel CPU pipeline background drove his desire for a clean, bug-free CPU implementation.
RISC-V's ISA Enables Lower Gate Count
- RISC-V's smaller ISA reduces instruction decoding complexity compared with ARM's multi-generation ISA.
- Fewer instructions translate to lower gate count and potential power savings at similar performance levels.
Early Collaboration With SiFive
- Jerry Chen began working with SiFive in 2017 on a CPU design service project because many SiFive engineers were ex-Intel.
- He found licensing SiFive cores a straightforward choice given that connection.