Cheeky Pint Reiner Pope of MatX on accelerating AI with transformer-optimized chips
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Feb 26, 2026 
Reiner Pope, co-founder and CEO of MatX and former Google TPU architect, explains why current AI chips hit a wall and how MatX rethinks memory and numerics. He discusses the latency vs throughput trade-off, combining HBM and SRAM, manufacturing at TSMC scale, and why Rust and mental iteration shape their design approach.
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Throughput Versus Latency Defines LLM Chip Value
- Throughput and latency are the two metrics that determine LLM economics, with throughput driving dollars-per-token and latency driving user engagement.
- MatX targets both by combining large-memory HBM for throughput and low-latency SRAM plus systolic arrays to place weights on SRAM and activations on HBM.
MatX Raised $500M To Ramp Production
- MatX raised a $500M Series B led by Jane Street and Situational Awareness to ramp manufacturing and supply chain for chip production.
- Reiner notes ~$100M is needed to produce small-volume chips and multi-gigawatt deployments require tens of billions in chips.
Prove Demand Before Locking Supply
- To scale a startup AI chip business, secure both deep technical validation and supply commitments so suppliers trust you'll be a lasting customer.
- MatX raised a $500M Series B and lined up buyers to prove demand to HBM and fab suppliers.