Asianometry VLIW: The “Impossible” Computer
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Apr 5, 2026 A tale of a seemingly impossible computer promising massive speedups using ordinary silicon. CPU basics are explained with a playful kitchen analogy. The story dives into instruction-level parallelism, trace scheduling, and the risky tricks compilers used to pack and backtrack code. It follows a daring academic startup building VLIW hardware, their initial wins, market struggles, and the lasting influence of their ideas.
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Trace Scheduling Breaks Block Boundaries
- Trace scheduling treats multiple basic blocks as one predicted long block and aggressively moves independent instructions up for parallel execution.
- If the predicted path is correct, this can yield 10–30x speedups compared with conservative block-level scheduling.
VLIW Moves Complexity To The Compiler
- VLIW shifts complexity from hardware to compiler, avoiding dynamic hardware mechanisms that resolve runtime mispredictions.
- The compiler inserts compensating code to backtrack when a predicted trace goes wrong, trading code size for simpler silicon.
Josh Fisher's ELI 512 Paper Sparked VLIW
- Josh Fisher developed the ELI 512 VLIW concept and published Very Long Instruction Word Architectures with the ELI 512 design.
- His paper paired the hardware idea with the Bulldog trace-scheduling compiler to realize massive parallelism.
